1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, more particularly to a structure of a lateral transistor suitable for implementing a high-density monolithic integration on a semiconductor substrate.
2. Description of the Related Art
A structure merging a power transistor and its control circuit on the same semiconductor chip so as to form a semiconductor integrated circuit is known. In such a power IC, sometimes the power transistor is made by a vertical npn transistor and the control circuit by lateral pnp transistors, the lateral pnp transistor operating with relatively lower power than the vertical npn transistor. An example of the structure of the earlier lateral pnp transistor employed in these semiconductor integrated circuits (power ICs) is shown in FIGS. 1A and 1B. That is, the earlier lateral pnp transistor embraces a semiconductor substrate 1, an n-type first buried region 22 formed on the semiconductor substrate 1, an n-type first base region 33 formed over the entire surface of the semiconductor substrate 1, an n-type first plug region 4 so formed that the bottom of the first plug region 4 reaches to the first buried region 22, a p-type first emitter region 6 and a p-type first collector region 7 formed in and at the surface of the first base region 33, and an n-type first base contact region 9 formed in and at the surface of the first plug region. The lateral pnp transistor constructed in this manner encompasses further a field insulating film 86 on the top surface. And, a first emitter wiring 11, a connecting wiring 12, and a first base wiring 14 contact through contact holes in the field insulating film 86 with the first emitter region 6, the first collector region 7 and the first base contact region 9. The connecting wiring 12 serves as a first collector wiring and is connected to the base electrode of the vertical npn transistor having a high maximum operating voltage, though the illustration of the vertical npn transistor is omitted in FIGS. 1A and 1B.
In the earlier semiconductor integrated circuit above mentioned, it is convenient for the fabrication process to construct the first base region 33 of the lateral pnp transistor and the drift region (collector region) of the high voltage vertical npn transistor with the same epitaxial layer having the same thickness and the same impurity concentration. Because the vertical npn transistor composed of a second emitter region, a second base region and a second collector region is disposed at the back of the plane of the cross section in FIG. 1A, the illustration of the vertical npn transistor is omitted. In this case, the impurity concentration of the first base region 33 of the lateral pnp transistor and of the drift region of the vertical npn transistor must be set to a relatively low value, since the vertical npn transistor is required to operate with a higher maximum operating voltage. Therefore, it is necessary to make a base width Wb of the lateral pnp transistor larger relatively in order to suppress the occurrence of xe2x80x9cthe depletion-layer punch-throughxe2x80x9d between the emitter and collector regions so as to maintain the higher breakdown voltage between the emitter and collector electrodes of the lateral pnp transistor.
However, when the base width Wb is increased in the lateral pnp transistor, the current gain decreases so as to degrade the electrical performances. Further, the occupied space of the lateral pnp transistor increases and results in undesirable lowering of the on-chip integration degree of the semiconductor elements.
In view of these situations, it is an object of the present invention to provide a lateral transistor, a semiconductor integrated circuit and a fabrication method thereof, capable of obtaining a required high breakdown voltage between the first and second main electrodes by decreasing the base width Wb. xe2x80x9cThe first main electrode regionxe2x80x9d is one of the emitter and collector regions of the bipolar transistor (BJT), if the lateral transistor is the lateral BJT. xe2x80x9cThe second main electrode regionxe2x80x9d is the other of the emitter and collector regions, if the lateral transistor is the lateral BJT. For example, if the first main electrode region is the emitter region, the second main electrode region is the collector region. Between the first and second main electrode regions, a main current controlled by the base region flows so as to form a current path between the first and second main electrode regions.
Another object of the present invention is to provide a lateral transistor, a semiconductor integrated circuit and a method of fabricating thereof, capable of decreasing the occupied area of the lateral transistor to increase the on-chip integration degree.
A further different object of the present invention is to provide a lateral transistor, a semiconductor integrated circuit and a method of fabricating thereof, capable of improving a current gain of the integrated lateral transistor.
A further different object of the present invention is to provide a lateral transistor, a semiconductor integrated circuit and a method of fabricating thereof, capable of forming a highly integrated lateral transistor by a simple process compared with the earlier fabricating method of the lateral transistor or the semiconductor integrated circuit and thus realizing a considerable cost down.
To achieve the above-mentioned objects, a first feature of the present invention lies in a lateral transistor encompassing: (a) a semiconductor substrate of the first conductivity type; (b) a buried region of the second conductivity type disposed on the semiconductor substrate; (c) a uniform base region of the second conductivity type disposed on the first buried region; (d) a plug region of the second conductivity type disposed in the uniform base region, the plug region protrudes from a top surface of the uniform base region so as to reach to the buried region; (e) first and second main electrode regions of the first conductivity type disposed in and at the top surface of the uniform base region; and (f) a graded base region of the second conductivity type disposed in the uniform base region, enclosing bottom and side of the first main electrode region, the graded base region has a doping profile such that impurity concentration decreases towards the second main electrode region from the first main electrode region. Here, the combination of the uniform base region and the graded base region serves as a base region. Here, xe2x80x9cthe first conductivity typexe2x80x9d and xe2x80x9cthe second conductivity typexe2x80x9d are opposite conductivity type each other. That is, when the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.
According to the first feature of the present invention, it is possible to increase the impurity concentration in the graded base region of the lateral transistor relatively, compared with earlier lateral transistor. Therefore, a desired high breakdown voltage between emitter and collector (BVceo) can be obtained by making the width of the graded base region Wb thinner compared with the earlier lateral transistor, if the lateral transistor is the lateral BJT. As the width of the graded base region Wb can be reduced, the occupied space of the lateral transistor decreases, so that the on-chip integration degree of the semiconductor integrated circuit can be increased. In addition to the reduced width of the graded base region Wb, an impurity concentration gradually decreasing from the first main electrode region to the second main electrode region achieves an optimum built-in drift field. Therefore, the transport efficiency of the carriers injected into the graded base region is increased, so that reduction of the base transit time may be obtained. Hence the current gain of the lateral transistor is improved.
A second feature of the present invention lies in a semiconductor integrated circuit including a lateral transistor, the lateral transistor encompassing: (a) a semiconductor substrate of the first conductivity type; (b) a first buried region of the second conductivity type disposed on the semiconductor substrate; (c) a uniform base region of the second conductivity type disposed on the first buried region; (d) a first plug region of the second conductivity type disposed in the uniform base region, the first plug region protrudes from a top surface of the uniform base region so as to reach to the first buried region; (e) first and second main electrode regions of the first conductivity type disposed in and at the top surface of the uniform base region; and (f) a graded base region of the second conductivity type disposed in the uniform base region, enclosing bottom and side of the first main electrode region, the graded base region has a doping profile such that impurity concentration decreases towards the second main electrode region from the first main electrode region. Here, the combination of the uniform base region and the graded base region serves as a first base region of the lateral transistor.
According to the second feature of the present invention, the base width is made narrower compared to the earlier lateral transistor, while keeping a higher required breakdown voltage between the collector and the emitter can be obtained. Further, according to the second feature, it is capable of developing the on-chip integration degree of the semiconductor integrated circuit by decreasing the occupied space for the lateral transistor. Further, according to the second feature, the current gain of the integrated lateral transistor can be improved.
A third feature of the present invention lies in a method of fabricating a semiconductor integrated circuit encompassing: (a) selectively forming a first diffusion region of the second conductivity type on a semiconductor substrate of a first conductivity type; (b) growing an epitaxial layer of the second conductivity type on the first diffusion region so as to make the first diffusion region a first buried region; (c) selectively diffusing impurity atoms of the second conductivity type so as to form a first plug region of the second conductivity type, from a top surface of the epitaxial layer such that a bottom of the first plug region reaches to the first buried region; (d) selectively diffusing impurity atoms of the second conductivity type so as to form a graded base region of the second conductivity type, from the top surface of the epitaxial layer, a lateral position of the graded base region is separated from the lateral position of the first plug region and a vertical position of the graded base region is separated from the vertical position of the first buried region, the graded base region has a doping profile such that impurity concentration decreases towards peripheral region from central region of the graded base region; (e) forming a first main electrode region of the first conductivity type in and at the top surface of the graded base region; and (f) forming a the second main electrode region of the first conductivity type, so as to sandwich the graded base region between the first and second main electrode regions, in and at the top surface of the epitaxial layer.
According to the third feature of the present invention, the graded base region formed before the formation of the first main electrode region is drove-in more deeply than the edge portion of the first main electrode region by the thermal treatment required for forming the first main electrode region. Therefore, the graded base region is formed adjacently to and surrounding the first main electrode region. It is possible to form the graded base region and the first main electrode region by the diffusion self-alignment (DSA) method using the same diffusion window. Accordingly, spreading widths of the graded base region extending laterally from the edge portions of the first main electrode region are equal in both directions and the gradient of the impurity profile can be made equal in both directions. When the graded base region is formed in ring shape surrounding the first main electrode region on the plane pattern, width of the ring-like graded base region can be formed uniformly. Therefore, formation of a highly integrated circuit with the lateral transistor by a simple process compared with the earlier method of fabricating a semiconductor integrated circuit is possible, so that considerable cost down is realized. xe2x80x9cThe diffusion windowxe2x80x9d may be a window provided in the silicon oxide film used for pre-deposition (vapor phase diffusion) or for ion implantation.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the present invention in practice.